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3.1.6.3 End of Initialization Bit (ENDINIT)
The ENDINIT bit is a control bit used to indicate that the user has completed all device and system level initialization tests,
and that the device will operate in normal mode. Once the ENDINIT bit is set, writes to all writable register bits are inhibited except
for the DEVCTL register. Once written, the ENDINIT bit can only be cleared by a device reset. The writable register CRC check
(reference Section 3.2.2 ) is only enabled when the ENDINIT bit is set.
When ENDINIT is set, the following occurs:
? Offset Cancellation is forced to normal mode. OCPHASE[1:0], and OFFCFG_EN remain in their previously set states.
? X-Axis Self Test is disabled. ST remains in its previously set state.
3.1.6.4 SD Bit
The SD bit determines the format of acceleration data results. If the SD bit is set to a logic ‘1’, unsigned results are transmitted,
with the zero-g level represented by a nominal value of 512. If the SD bit is cleared, signed results are transmitted, with the zero-
g level represented by a nominal value of 0.
SD
1
0
Operating Mode
Unsigned Data Output
Signed Data Output
3.1.6.5 OFMON Bit
The OFMON bit determines if the offset monitor circuit is enabled. If the OFMON bit is set to a logic ‘1’, the offset monitor is
enabled. Reference Section 3.8.5 . If the OFMON bit is cleared, the offset monitor is disabled.
OFMON
1
0
Operating Mode
Offset Monitor Circuit Enabled
Offset Monitor Circuit Disabled
If the OC bit in the DEVCFG register is cleared (Offset Cancelled Data), then the Offset Monitor is automatically enabled (OF-
MON = ‘1’) regardless of the value written to DEVCFG[3].
3.1.6.6 ARM Configuration Bits (A_CFG[2:0])
The ARM Configuration Bits (A_CFG[2:0]) select the mode of operation for the ARM/PCM pins.
Table 9. Arming Output Configuration
A_CFG[2]
0
0
0
0
1
1
1
1
A_CFG[1]
0
0
1
1
0
0
1
1
A-CFG[0]
0
1
0
1
0
1
0
1
Operating Mode
Arm Output Disabled
PCM Output
Moving Average Mode
Moving Average Mode
Count Mode
Count Mode
Unfiltered Mode
Unfiltered Mode
Output Type
Hi Impedance
Digital Output
Active High with Pulldown Current
Active Low with Pullup Current
Active High with Pulldown Current
Active Low with Pullup Current
Active High with Pulldown Current
Active Low with Pullup Current
Reference
Section 3.8.11
Section 3.8.10.1
Section 3.8.10.1
Section 3.8.10.2
Section 3.8.10.2
Section 3.8.10.3
Section 3.8.10.3
MMA655x
Sensor
Freescale Semiconductor, Inc.
15
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